When supply voltages on the order of 1.8 V are to be attained, the use of inverting amplifiers with an active load becomes necessary. These inverting amplifiers require a circuit capable of providing the appropriate bias voltage. Moreover, active load inverters have the advantage of allowing a high voltage and a temperature controlled biasing of the memory bit line if the dimensions of the transistor used as the inverter are appropriately chosen.
The bias circuit, however, requires a very large capacitor for coupling to the power supply for noise rejection. The circuit must therefore be able to drive large capacitive loads and must be allowed to reach a steady-state current value without current overshooting. This might cause malfunctions during the first reading of the memory after its power-on.
The circuit must also be able to power on in a very short time so that it is possible to switch off all the circuits related to the sense amplifier. This minimizes power consumption without penalizing the speed with which the first reading of the memory occurs.
Conventional circuits capable of providing a bias voltage are usually provided by current mirror structures which start from the reference current and achieve the intended bias current by a multiplication factor. A typical conventional structure is shown in FIG. 1, which is formed by a diode connected P-channel transistor P1 and an N-channel transistor N1 is connected in series. The transistors P1 and N1 are connected between a supply voltage Vdd and ground. A capacitor C is connected between the gate terminal of the transistor P1 and the supply voltage Vdd.
If the circuit shown in FIG. 1 must drive large capacitive loads C, it can be rendered very fast if the node VIPSENSE is precharged to the ground value at the beginning of each power-on. The main drawback of the circuit of FIG. 1 is that this optimization is very difficult to provide for all kinds of processes, temperatures, models and supply voltages.
If the circuit is optimized for a supply voltage of 3 V, for example, while avoiding current overshooting, then the risk arises for making the circuit too slow at lower voltages, such as 1.8 V. The opposite is also true if the circuit is rendered fast enough for a supply voltage Vdd equal to 1.8 V, there is the risk of providing current overshooting for Vdd equal to 3 V. On the other hand, if the node VIPSENSE is made to start from a value which is close to the steady-state value, it is still necessary to place many buffers in parallel to each other to charge the capacitor C rapidly enough.